FIG. 7 shows the configuration of a conventional A/D converter. The A/D converter shown in FIG. 7 is a full-flash A/D converter and includes a referential voltage generation circuit 601, a differential amplifier circuit row 602, a voltage comparison circuit row 603, and an encoder 605.
The referential voltage generation circuit 601 divides a voltage between a high-voltage reference voltage supplied to a high-voltage terminal 601H and a low-voltage reference voltage supplied to a low-voltage terminal 601L by m+1 resistors R1 to Rm+1, thereby generating m+1 referential voltages VR1 to VRm+1. The generated referential voltages VR1 to VRm+1 are input to the differential amplifier circuit row 602. The differential amplifier circuit row 602 has m+1 differential amplifier circuits A1 to Am+1. Each of these differential amplifier circuits simultaneously amplifies a differential voltage between an analog signal voltage AIN input from an analog signal voltage input terminal 604 and a corresponding one of the referential voltages VR1 to VRm+1 and outputs a positive output voltage and a negative output voltage, which are complementary voltages. The voltage comparison circuit row 603 has m+1 voltage comparison circuits Cr1 to Crm+1. Each of these voltage comparison circuits Cr1 to Crm+1 simultaneously compares the magnitudes of the positive and negative output voltages from a corresponding one of the differential amplifier circuits provided in the previous stage. The encoder 605 converts the m+1 comparison results output from the voltage comparison circuit row 603 and outputs a digital data signal DOUT having a predetermined resolution from a digital data output terminal 606.
The conventional A/D converter having the above-described parallel structure has the advantage of being capable of performing high-speed A/D conversion over various A/D converters, such as integrating A/D converters, serial-parallel A/D converters, and pipeline A/D converters, while having a disadvantage in that as the resolution increases, the number of differential amplifier circuits and the number of voltage comparison circuits are increased to cause the A/D converter to consume more power and occupy a larger area.
As an A/D converter in which this disadvantage has been overcome, a technique is disclosed in Patent Document 1, for example, in which voltage interpolation is performed by dividing the outputs of differential amplifier circuits by resistors or the like. In this technique, a voltage between the output voltages of each two adjacent differential amplifier circuits is interpolated, and the interpolated voltages are used in voltage comparison by voltage comparison circuits. Thus, as compared with a case in which no interpolation is performed, the number of differential amplifier circuits decreases by a factor of the interpolation bits, thereby reducing the power consumption and the occupied area.
Furthermore, an A/D converter which uses dynamic voltage comparison circuits as voltage comparison circuits is also disclosed by Patent Document 2, for example, as an A/D converter in which power consumption is reduced further. In this technique, dynamic voltage comparison circuits which do not need a constant current are used in place of high-speed operation, highly-responsive, constant-current voltage comparison circuits which are used in typical A/D converters, thereby enabling a significant reduction in power consumption.
In recent years, as semiconductor devices have been downsized, power supply voltage has been set at low levels. As a result, the input dynamic range of voltage comparison circuits has narrowed, imposing limits on the output dynamic range of differential amplifier circuits. This produces a problem in that due to variations in power supply voltage, in temperature, and in transistor characteristics, etc., the output dynamic range of the differential amplifier circuits changes and no longer matches the input dynamic range of the voltage comparison circuits, causing degradation of the accuracy of the A/D converter.
As an A/D converter in which this problem has been overcome, Patent Document 3, for example, discloses a technique for adjusting the output dynamic range of differential amplifier circuits to the input dynamic range of voltage comparison circuits. FIG. 8 shows the configuration of the A/D converter disclosed in Patent Document 3. The A/D converter shown in FIG. 8 is a full-flash A/D converter and includes a referential voltage generation circuit 701, a differential amplifier circuit row 702, a voltage comparison circuit row 703, an encoder 705, and an adjusting circuit 707.
The referential voltage generation circuit 701 divides a voltage between a high-voltage reference voltage supplied to a high-voltage terminal 701H and a low-voltage reference voltage supplied to a low-voltage terminal 701L by m+1 resistors R1 to Rm+1, thereby generating m+1 referential voltages VR1 to VRm+1. The generated referential voltages VR1 to VRm+1 are input to the differential amplifier circuit row 702. The differential amplifier circuit row 702 has m+1 differential amplifier circuits A1 to Am+1. Each of these differential amplifier circuits A1 to Am+1 simultaneously amplifies a differential voltage between an analog signal voltage AIN input from an analog signal voltage input terminal 704 and a corresponding one of the referential voltages VR1 to VRm+1 and outputs a positive output voltage and a negative output voltage, which are complementary voltages. The voltage comparison circuit row 703 has m+1 voltage comparison circuits Cr1 to Crm+1. Each of these voltage comparison circuits Cr1 to Crm+1 simultaneously compares the magnitudes of the positive and negative output voltages from a corresponding one of the differential amplifier circuits provided in the previous stage. The encoder 705 converts the m+1 comparison results output from the voltage comparison circuit row 703 and outputs a digital data signal DOUT having a predetermined resolution from a digital data output terminal 706. The configuration discussed so far is the same as the configuration of the previously described A/D converter.
The adjusting circuit 707, which is the key feature of the technique disclosed in Patent Document 3, includes a differential amplifier circuit replica 708, a voltage comparison circuit replica 709, a reference voltage output circuit 710, an operational amplifier circuit 711, an average voltage generation circuit 712, and a low pass filter 717. The differential amplifier circuit replica 708 has the same structure as the differential amplifier circuits A1 to Am+1 that form the differential amplifier circuit row 702. Two input voltages to the differential amplifier circuit replica 708 are the same voltage Vo, and the differential amplifier circuit replica 708 outputs a differential amplifier circuit common mode voltage 713. The voltage comparison circuit replica 709 has the same structure as the voltage comparison circuits Cr1 to Crm+1 that form the voltage comparison circuit row 703. The differential amplifier circuit common mode voltage 713 is input to the voltage comparison circuit replica 709. And a positive output voltage and a negative output voltage from the voltage comparison circuit replica 709 are input to average voltage generation resistors a712a and b712b, respectively, in the average voltage generation circuit 712, and a voltage comparison circuit common mode voltage 714, which is the average voltage of those positive and negative output voltages, is obtained. The reference voltage output circuit 710 outputs a reference voltage 715 falling within a predetermined range including the voltage comparison circuit common mode voltage 714 when the output dynamic range of the differential amplifier circuits A1 to Am+1 and of the differential amplifier circuit replica 708 is within the input dynamic range of the voltage comparison circuits Cr1 to Crm+1 and of the voltage comparison circuit replica 709. The operational amplifier circuit 711 receives the voltage comparison circuit common mode voltage 714 output from the average voltage generation circuit 712 and the reference voltage 715 output from the reference voltage output circuit 710 and outputs a feedback control voltage 716 so that the voltage comparison circuit common mode voltage 714 and the reference voltage 715 match. The feedback control voltage 716 is connected to the low pass filter 717. The low pass filter 717, which is composed of a filter resistor 717R and a filter capacitor 717C, removes a high-frequency component from the feedback control voltage 716 to obtain a post-low-pass-filtering feedback control voltage 718. The post-low-pass-filtering feedback control voltage 718 is fed back to the differential amplifier circuit replica 708 and to the differential amplifier circuits A1 to Am+1.
The reference voltage output circuit 710 includes a reference voltage generation circuit 719, a decoder 720, and a selection circuit 721. The reference voltage generation circuit 719 includes one or more voltage generation circuits 722 represented by reference marks Vref1 to Vrefn. Each voltage generation circuit 722 generates a different voltage that can be the reference voltage 715, and the generated voltage is connected with a corresponding one of the taps of the selection circuit 721. The decoder 720 receives an externally supplied control signal 723 indicated by a reference mark CS and outputs a selection signal 724 for controlling the selection circuit 721 according to the control signal 723. Thus, the reference voltage 715 is adjustable by the control signal 723.
The voltage comparison circuits Cr1 to Crm+1 have a circuit configuration shown in FIG. 3, for example. This circuit is a dynamic voltage comparison circuit characterized by high-speed operation and low power consumption, and the detailed operation thereof will be described later. On the other hand, the voltage generation circuits 722 disclosed in Patent Document 3 has a circuit configuration shown in FIG. 9, for example. This is almost the same as the configuration of the voltage comparison circuits Cr1 to Crm+1. The differences between the voltage comparison circuits Cr1 to Crm+1 and the voltage generation circuits 722 are as follows: an input transistor section 301 in the voltage comparison circuits Cr1 to Crm+1, which is composed of NMOS transistors, is replaced in the voltage generation circuits 722 with a resistor section 801 composed of two resistors R0a and R0b; a positive feedback section 302 in the voltage comparison circuits Cr1 to Crm+1 is replaced with a diode connection section 802 in the voltage generation circuits 722; reset sections 303 in the voltage comparison circuits Cr1 to Crm+1 are replaced with switch sections 803; and the gate terminals of the transistors forming the reset sections 303 in the voltage comparison circuits Cr1 to Crm+1 are connected with a clock terminal CLK, while the gate terminals of the transistors forming the switch sections 803 in the voltage generation circuits 722 are connected with a signal, which is always at the “High” level when the A/D converter operates. The gate terminal of a PMOS transistor m3a is connected to a reference voltage output terminal VREF.
The two resistors R0a and R0b in each voltage generation circuit 722 are connected at one end thereof to the source terminals of NMOS transistors m1a and m1b, respectively, of the diode connection section. The other end of each of the two resistors R0a and R0b in the voltage generation circuit 722 is connected with a ground voltage VSS. If the values of the two resistors R0a and R0b in each voltage generation circuit 722 included in the reference voltage generation circuit 719 differ from one voltage generation circuit 722 to another, the voltage generation circuits 722 can produce different voltages.
The configuration described above enables the output dynamic range of the differential amplifier circuits to accurately fall within the input dynamic range of the voltage comparison circuits, even if power supply voltage, temperature, transistor characteristics, or the like vary. It is thus possible to prevent the accuracy of the A/D converter from decreasing due to those variations. In addition, the reference voltage 715 is adjusted according to the received external control signal 723, whereby the operation margin can be increased further.    Patent Document 1: Japanese Laid-Open Publication No. 4-43718    Patent Document 2: Japanese Laid-Open Publication No. 2003-158456    Patent Document 3: Japanese Laid-Open Publication No. 2006-87064